1. Field of the Invention
The present invention relates to an input receiver circuit for receiving a high-speed input signal representing one datum of a plurality of data in each of successive input clock intervals and for outputting a plurality of output signals which can be processed at a lower acquisition speed compared to the speed of the high-speed input signal, and each of which represents one datum of the plurality of data within an output clock interval.
2. Description of the Related Art
In numerous applications, in particular in data transmission, data storage and data processing, data serially coded by an input signal with a high-speed or transfer speed or data transfer rate have to be received and processed. In doing so, it is often desirable to acquire and process further the data with an acquisition speed lower than the transmission speed of the input signal.
For this purpose, a serial-to-parallel converter is conventionally used which receives data, which are serially coded in an input signal, and outputs them in parallel coded in a plurality of output signals.
FIG. 3 is a schematic circuit diagram of a conventional serial-to-parallel converter. The serial-to-parallel converter receives an input signal data at an input 10 and an input clock signal clock at a clock signal input 12. The serial-to-parallel converter outputs output signals representing data Q0, Q1, Q2, Q3 at the outputs 14, 16, 18, 20 in parallel fashion. Furthermore, the serial-to-parallel converter outputs an output clock signal clock/4 at a clock signal output 22.
The input clock signal is periodic and usually has a fixed clock frequency. Rising or falling edges of the input clock signal clock define successive input clock intervals or the limits thereof. The input signal data represents a sequence of data, the input signal data representing in each input clock interval a datum, for example a bit of a binary notation of a letter or of a number or of other information.
The output clock signal clock/4 is also periodic, its output clock frequency being a quarter of the input clock frequency of the input clock signal clock. Rising or falling edges of the output clock signal clock/4 define output clock intervals. The output signals Q0, Q1, Q2, Q3 represent data which the serial-to-parallel converter has received at the input 10 in the form of the input signal. In an output clock interval the output signals Q0, Q1, Q2, Q3 each represent a datum the serial-to-parallel converter has previously received by the input signal in four successive input clock intervals.
The serial-to-parallel converter includes four D-flip-flops 24, 26, 28, 30. Each of the D-flip-flops 24, 26, 28, 30 has an input D, a clock signal input C and an output Q. The clock signal inputs C of all D-flip-flops 24, 26, 28, 30 are connected to the clock signal input 12 of the serial-to-parallel converter to receive the input clock signal clock. The input D of the first D-flip-flop 24 is connected to the input 10 of the serial-to parallel converter. The output Q of the first D-flip-flop 24 is connected to the input D of the second D-flip-flop 26, the output Q of the second D-flip-flop 26 is connected to the input D of the third D-flip-flop, the output Q of the third D-flip-flop 28 is connected to the input D of the fourth D-flip-flop 30.
The serial-to-parallel converter further includes four memories 32, 34, 36, 38 which are also realized as D-flip-flops in this example. Each of the memories 32, 34, 36, 38 has an input D, a clock signal input C and an output Q. The input D of the first memory 32 is connected to the output Q of the first D-flip-flop 24, the input D of the second memory 34 is connected to the output Q of the second D-flip-flop 26, the input D of the third memory 36 is connected to the output Q of the third D-flip-flop 28 and the input D of the fourth memory 38 is connected to the output Q of the fourth D-flip-flop 30. The output Q of the fourth memory 38 is connected to the first output 14 of the serial-to-parallel converter, the output Q of the third memory 36 is connected to the second output 16 of the serial-to-parallel converter, the output Q of the second memory 34 is connected to the third output 18 of the serial-to-parallel converter and the output Q of the first memory 32 is connected to the fourth output 20 of the serial-to-parallel converter.
The serial-to-parallel converter further includes a frequency divider 40 having an input In and an output Out. The input In of the frequency divider 40 is connected to the clock signal input 12 of the serial-to-parallel converter in parallel to the clock signal inputs C of the D-flip-flops 24, 26, 28, 30, to receive the input clock signal clock. The output Out of the clock divider 40 is connected in parallel to the clock signal inputs C of the memories 32, 34, 36, 38 and to the clock signal output 22 of the serial-to-parallel converter. The clock divider 40 generates the output clock signal clock/4 whose output clock frequency is one quarter of the input clock frequency from the input clock signal clock.
The four D-flip-flops 24, 26, 28, 30 represent a shift register in which each datum of the input signal data is successively pushed through all D-flip-flops 24, 26, 28, 30. In each input clock interval, each D-flip-flop, 26, 28, 30 obtains the datum that was present in the previous D-flip-flop 24, 26, 28 in the previous input clock interval. Controlled by the output clock signal clock/4, after four input clock intervals the memories 32, 34, 36, 38 take over the data that are stored in the D-flip-flops 24, 26, 28, 30 at this time. As described above, at the end of respective four input clock intervals, output signals Q0, Q1, Q2, Q3 which the input signal data represented in the four input clock intervals serially are available in parallel at the outputs 14, 16, 18, 20 of the serial-to-parallel converter.
The sampling of a signal, for example of the input signal data of the serial-to-parallel converter illustrated in FIG. 3, needs a sampling time basically consisting of a setup time or initialization time or setting time and a hold time or holding time or a take over time. The setup time is the minimum period of time during which the signal to be sampled must be stable or unchanged before it is sampled. The hold time is the minimum period of time necessary for the sampling of the signal and during which the signal to be sampled must also be stable or unchanged. Both setup time and hold time depend, among other things, on the signal to be sampled, in particular on its signal level and its noise level, as well as on the sampling circuit.
In the conventional serial-to-parallel converter illustrated above using FIG. 3, setup time and hold time are limited by the length of an input clock interval, or, to be more accurate, by the period of time within an input clock interval within which the input signal data has a substantially constant signal level. The higher the data transmission rate of the input signal data or the input clock frequency of the input clock signal clock is, the shorter setup and hold time of the D-flip-flops 24, 26, 28, 30 have to be. However, the shorter setup and hold time of a circuitry are, the higher the development effort, production costs and power requirements thereof are as a rule. One disadvantage of the conventional serial-to-parallel converter illustrated by using FIG. 3 is thus that an increase of the transmission rate results in an increase of the costs of purchase and operation of the serial-to-parallel converter. This is even made worse by that all four D-flip-flops 24, 26, 28, 30 have to have the same short setup and hold times. The memories 32, 34, 36, 38 also have to accept the data from the D-flip-flops 24, 26, 28, 30 within a single input clock interval. Thus the setup and hold times of the memories 32, 34, 36, 38 cannot be longer than those of the D-flip-flops 24, 26, 28, 30 either.
In addition to that, the conventional serial-to-parallel converter illustrated by using FIG. 3 comprises a marked tendency towards bit errors, in particular when data and clock are transmitted over the same channel or when the input signal is noisy or has a high noise level. However, in many applications, namely in high-speed applications, the input signal has a high noise level.
The conventional serial-to-parallel converter illustrated in FIG. 3 is thus hardly suitable for receiving high-speed input signals or not at all. If at all, it is only adaptable to a high-speed application with a high effort in terms of circuit engineering and at the cost of high supply power requirements.
At the same time, the conventional serial-to-parallel converter has properties which are not of interest for many applications. These include, for example, the exact parallelity of the output signals. However, some of the development efforts, the production costs and the supply power requirements can be attributed to these properties.